1. Technical Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof, and in particular to a semiconductor device wherein a structure of a silicon spacer for SiP (System in a Package) provided with conductive plugs penetrating through a substrate has been improved and a manufacturing method thereof.
2. Description of the Related Art
With the downsizing and advancement in performance of electronic appliances, downsizing and multifunctionality have been demanded for semiconductor devices to be mounted on electronic appliances as well. As methods for realizing multifunctionality of a semiconductor device, a method of planarly arranging a plurality of semiconductor chips and connecting these by TAB (tape automated bonding) and a method of laminating a plurality of semiconductor chips in the thickness direction for connection exist, wherein for realization of downsizing, the method of laminating semiconductor chips in the thickness direction is excellent.
Herein, when two semiconductor chips are laminated in the thickness direction, a method of forming electrodes on the respective semiconductor chips and opposing and adhering both semiconductor chips to each other via solder balls (so-called face-down bonding) or the like is used. While when three or more semiconductor chips are laminated, a semiconductor device provided with conductive plugs penetrating through a semiconductor substrate (a so-called silicon spacer) is used (for example, Japanese Published Unexamined Patent Application No. H10-223833 (Pages 5 to 12, FIG. 4)).
A prior-art semiconductor device described in this publicly known document will be described with reference to the drawings. First, as shown in FIG. 1A, on a silicon substrate 1 inside for which a desirable element has been formed in advance and on whose surface a first interlayer insulating film 10 of a silicon nitride film has been formed, a mask pattern 11 of a silicon oxide film is formed, and the first interlayer insulating film 10 and the silicon substrate 1 are etched by an RIE method using an Fluorine-based gas, whereby holes 4 with a predetermined depth penetrating through the first interlayer insulating film 10 are formed.
Next, as shown in FIG. 1B, by use of an LPCVD method, a silicon oxide film and a silicon nitride film are deposited in order on the entire surface of the silicon substrate 1, whereby a laminated insulating film 12 of a laminated structure is formed on the first interlayer insulating film 10 and on inner walls and bottom portions of the holes 4.
Next, as shown in FIG. 1C, by use of a CVD method, a sputtering method, a plating method and the like, after a conductive material such as W (tungsten), Mo (molybdenum) or the like to be conductive plugs is deposited on the entire surface of the silicon substrate 1 and the insides of the holes 4 are buried with the conductive material, by use of a CMP method, an etchback method or the like, the conductive material and laminated insulating film 12 are etched until the first interlayer insulating film 10 is exposed to form conductive plugs 5a. 
Next, as shown in FIG. 1D, a multi-layer wiring structure 13 composed of metal wiring, an interlayer insulating film, plugs, etc., is formed on the silicon substrate 1. Thereafter, grooves are formed on the surface of the multi-layer wiring structure 13, and pads 14 are formed in these grooves.
Next, as shown in FIG. 1E, by use of CMP, chemical polishing, mechanical polishing, wet etching, dry etching, or the like, the surface on the side opposite (rear-surface side) to the surface on which the holes 4 have been formed is polished or ground until the laminated insulating film 12 on the bottom portions of the holes 4 is exposed.
Next, as shown in FIG. 1F, a silicon oxide film 15 is formed on the entire surface of the rear surface of the silicon substrate 1 by use of a plasma CVD method. At this time, if a low-temperature process is required, an SOG film is formed in place of the silicon oxide film 15, or if a reduction in stress which the silicon substrate 1 receives is demanded, an organic film such as a polyimide film is formed in place of the silicon oxide film 15.
Next, as shown in FIG. 1G, the silicon oxide film 15 and laminated insulating film 12 are polished by use of a CMP method until the conductive plugs 5a are exposed. Thereby, a semiconductor device (silicon spacer) wherein the conductive plugs 5a have been embedded in the through holes via the laminated insulating film 12 is completed.
As such, for forming a semiconductor device (silicon spacer) of the above-described structure, it is necessary, after forming the conductive plugs 5a on the front-surface side of the silicon substrate 1, to grind the rear-surface side of the silicon substrate 1 by a CMP method or the like, and furthermore, after forming the insulating film such as a silicon oxide film 15 on the rear-surface side, to grind the insulating film to expose the surfaces of the conductive plugs 5a. However, if the rear surface grinding and insulating film formation are carried out without reinforcing the silicon substrate 1, inconveniences occur such that the silicon substrate 1 is damaged and the properties of the element formed inside are changed, and moreover, workability is inferior. Therefore, normally, employed is a method wherein, after forming the conductive plugs 5a, a support composed of a glass substrate or the like is adhered to the front-surface side of the silicon substrate 1, grinding or polishing of the rear-surface side of the silicon substrate 1, formation of an insulating film, grinding or polishing of the insulating film are carried out, and thereafter, the support is removed.
However, since adhesives are generally easily affected by heat, when forming an insulating film on the rear-surface side of the silicon substrate 1 to which a support has been fixed by an adhesive, film forming temperature thereof must be lowered. Therefore, the formed insulating film is weak in mechanical strength, and inconveniences occur such that the insulating film is exfoliated in the CMP step of the insulating film for exposing the conductive plugs, and minute flaws called scratches are produced.
In addition, in the foregoing publicly known document, although there is a description to the effect that a coated film such as an SOG film is preferably used in place of the silicon oxide film 15 when a low-temperature process is required, since the SOG film is weak in mechanical strength of the film and adhesion to the silicon substrate 1 is also inferior, exfoliation eventually occurs in the CMP step. In addition, if the SOG film is merely baked at low temperature, since a dehydration/condensation reaction of the SOG is not sufficiently carried out, it results in a hygroscopic film with much leakage.